Gelsinger was hired as a known long time engineer, rather than as a business expert. I would trust his numbers from an engineering perspective, even though I was laid off under his rule
All depends on the maturity of the process. 10% for a new design on a bleeding edge process is possibly viable. You’ll then tweak the design and process to get the yield up.
If you have a chip that is 50% of the wafer area, a single fault will lead to a yield of 50%. Now compare it with a chip that is 1% of the wafer area, the same single fault gets a yield of 99%.
So comparing the yields of two processes without factoring in the die area is not a fair game.
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Gelsinger was hired as a known long time engineer, rather than as a business expert. I would trust his numbers from an engineering perspective, even though I was laid off under his rule
All depends on the maturity of the process. 10% for a new design on a bleeding edge process is possibly viable. You’ll then tweak the design and process to get the yield up.
Only exception would be if they can produce those wafers at 1/10th of the previous cost, but I highly doubt that’s the case.
If it’s 1/10 of the cost of purchasing them from TSMC, it’s viable
Yield over die area should be the metric.
If you have a chip that is 50% of the wafer area, a single fault will lead to a yield of 50%. Now compare it with a chip that is 1% of the wafer area, the same single fault gets a yield of 99%.
So comparing the yields of two processes without factoring in the die area is not a fair game.